形式等価判定
1. Formal equivalence checkingFormal equivalence checking process is a part of electronic design automation (EDA), commonly used during the development of digital integrated circuits, to formally prove that two representations of a circuit design exhibit exactly the same behavior.
Read “Formal equivalence checking” on English Wikipedia
Read “形式等価判定” on Japanese Wikipedia
Read “Formal equivalence checking” on DBpedia
Read “Formal equivalence checking” on English Wikipedia
Read “形式等価判定” on Japanese Wikipedia
Read “Formal equivalence checking” on DBpedia
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